An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder
Li-Hsun Chen, O.T.-C. Chen, Teng-Yi Wang, Chi-Lung Wang · 2004
An adaptive digital signal processor (DSP) is proposed to realize the MPEG-4 video encoder at a high ratio of computation power versus hardware cost. First, software analyses are performed on the MPEG-4 video encoder, looking at the function and instruction levels. Analytical results from the function-level analysis show that the motion estimation inside the MPEG-4 video encoder has high computational complexity. As for the instruction-level analysis on the MPEG-4 video encoder without motion estimation, results reveal that the DSP equipped with 5 arithmetic logic units (ALUs), 1 multiplier and 2 Load/Store units has a higher computation performance than the other architectures with 8 functional units. Furthermore, the design of the adaptive mechanism can be incorporated in the said functional units. The suggestion is to group 4 ALUs and a multiplier into a special functional unit to exclusively process motion estimation. With the fact that a multiplier can be constructed by using multiple adders, the adaptable structure is also designed so that the numbers of adders and multipliers required can be dynamically changed to increase parallelism capability of local instructions, especially in discrete cosine transform and inverse discrete cosine transform. In comparing to conventional DSPs, the proposed adaptive DSP shows the best ratio of computation power over hardware cost to realize the MPEG-4 video encoder.