Restricted moduli Symmetrical quaternary signed-digit addition: A design implementation overview
Michael Naseimo Daikpor, Oluwole Adegbenro · International Conference on Systems, Signals and Image Processing · 2011
In this paper we present an overview of design implementation of a Symmetrical Multiple Valued Logic (SMVL) arithmetic circuit based on the use of restricted moduli Symmetrical Signed Residue Number System (SSRNS). Restricted radix-7 Symmetrical quaternary Signed digit (Rr7SqSd) T-gate based interconnections and full adders are used to implement sign detection, overflow detection and magnitude comparison without recourse to Mixed Radix number System (MRS) converters design or Chinese Remainder Theorem (CRT) computation.