Sandblaster Low-Power Multithreaded SDR Baseband Processor
John Glossner, Michael Schulte, Mayan Moudgill, Daniel Iancu, Sanjay Jinturkar, Tanuj Raja, Gary Nacer, Stamatis Vassiliadis · 2004
General-purpose processors have utilized complex and energy inefficient techniques to accelerate performance. In embedded DSP designs, power constraints have precluded general-purpose microarchitectural techniques. Rather than minimize average execution time, embedded DSP processors require the worst-case execution time to be minimized. Subsequently, Very Long In-struction Word (VLIW) processors have been employed, but architecturally visible side effects have imposed restrictions on parallelism due to interrupt and latency considerations – particu-larly if all loads must complete prior to servicing interrupts. In this paper, we present a low-power multithreaded interlocked (transparent) processor capable of parallelizing non-associative DSP arithmetic. We describe specific memory and logic tech-niques for reducing power dissipation and discuss how multi-threading enables low-power optimization. We further describe the programming environment for our SDR DSP processor. Fi-nally, we present automated results for complete physical layer processing of a number of communications protocols including WCDMA, GSM/GPRS, WLAN, and GPS. 1.