An Efficient Implementation of Search Trees on [lg N + 1] Processors
Carey, Thompson · IEEE Transactions on Computers · 1984
A scheme for maintaining a balanced search tree on γlg N + 1γparallel processors is described. The scheme is almost fully pipelined: γlg N + 1γ/2 search, insert, and delete operations may run concurrently. Each processor executes 0(1) instructions of a top-down 2-3-4 tree manipulation algorithm before passing the operation along to the next processor in the pipeline. Thus, the total delay per tree operation is O(lg N), and one tree operation completes every 0(1) time units.