A scheme for implementing address translation storage buffers
A.H. Mohamed, Assim A. Sagahyroon · 2003
In this paper we present a novel and efficient scheme to implement address translation storage buffers (TSBs). A TSB is tin operating system data structure that caches the most recent address translations. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement.