Parallel decoding architectures for low density parity check codes
C. Howland, Andrew Blanksby · 2002
A parallel architecture for decoding low density parity check (LDPC) codes is proposed that achieves high coding gain together with extremely low power dissipation, and high throughput. The feasibility of this architecture is demonstrated through the design and implementation of a 1024 bit, rate-1/2, soft decision parallel LDPC decoder.