A step towards intelligent translation from high-level design to RTL
Jean‐Pierre David, Étienne Bergeron · IEEE International Workshop on System-on-Chip for Real-Time Applications · 2004
Many researches have progressed to elaborate high level languages for system design. Nevertheless automatic refinement from high level to RTL can still not be automated and if designers can now specify their system at a high level, they are still forced to manually implement its RTL representation or use IP. We have developed an intermediate level language based on the representation of ASM charts with extensions such as user defined operators, communication channels, generic calls and recursivity but near the RTL level. This paper describes our compiler and presents our latest compilation results: the recursive Towers of Hanoi algorithm, various sort algorithms (included quick sort) and a mix of heap and merge sorts to implement fast parallel sort. These algorithms have been automatically synthesized in a FPGA and offer one to three orders of magnitude improvement compared to a pure software implementation for NoC. The tool is easily accessible to software or hardware designers and people from both communities will appreciate its high-level and cycle accurate approach.