Hardware interval multipliers.
Michael Schulte · 1996
This paper presents serial and parallel hardware units for interval multiplication. Compared to software implementations, these units greatly increase the performance of interval multiplication by providing automatic interval endpoint selection and correct rounding of the results. Area and delay estimates show that compared to a conventional IEEE multiplier, the serial interval multiplier requires only 15 percent more area and has a worst case delay that is five percent longer. Depending on the input operands, it requires either two or five cycles to compute the interval product. The parallel interval multiplier uses dual multipliers to compute two interval endpoints simultaneously. It has the same worst case delay as the serial interval multiplier, yet requires only one or three cycles to compute the interval product. Compared to previous hardware interval multipliers, our designs are one to three times faster and require less area.