AS/400 64-bit powerPC-compatible processor implementation
John M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein · 2002
An implementation of the 64-bit PowerPC Architecture optimized for the IBM AS/400 commercial environment is described. This 64-bit BiCMOS semicustom implementation runs at a clock rate of 170 MHz. The processor features a 4-way superscalar pipelined fixed point unit which can dispatch and execute up to 4 instructions each cycle, a floating point unit with a peak rate of 500 MFLOPs, 8-Kbyte L0 instruction cache, 256-Kbyte L1 cache, and support for 64-Gbyte of main storage. A 4-way rightly-coupled symmetric multi-processor system is one of several configurations supported by this implementation.>