IBM single chip RISC processor (RSC)
Charles R. Moore, D.M. Balser, J.S. Muhich, R.E. East · 2003
A highly integrated single-chip microprocessor is described that combines a powerful RISC architecture and superscalar machine organization with system design optimizations appropriate for low cost workstation applications. This RISC single-chip (RSC) processor can dispatch up to two instructions per cycle and concurrently execute up to three instructions per cycle. The design integrates a fixed-point execution unit, a floating-point execution unit, an in-page branch unit, an 8-Kbyte unified cache, a memory management unit, a DMA controller, an interrupt controller, ECC on the memory interface, a real-time clock and decrementer, built-in self-test, and a versatile engineering support processor interface on a single die.>