A methodology to design efficient BIST test pattern generators
Chih-Ang Chen, Sandeep K. Gupta · 2002
This paper describes a new technique to design efficient test pattern generators (TPGs) for built-in self-test (BIST). The proposed technique identifies compatible circuit inputs that can be connected to the same TPG stage in the test mode. Compatibility between circuit inputs is determined by analyzing the circuit function to guarantee coverage of all faults in a given target fault set. Unlike pseudo-exhaustive testing, circuit inputs that fanout to the same output can be compatible, provided that connecting them to the same TPG stage does not cause any loss of fault coverage. Experimental results show that TPGs designed by the proposed technique achieve 100% stuck-at fault coverage in practical test length (/spl les/2/sup 28/) with low hardware overhead and performance penalty for a wide range of benchmark circuits.