Test generation for MOS circuits
Harry H. Chen, Robert G. Mathews, John A. Newkirk · International Test Conference · 1984
Test generation for transistor switch faults is considered for nMOS combinational circuits. Examination of fault effects shows that memory and non-digital signals can result. A test strategy that accounts for MOS physical properties such as charge storage and bidirectionality is developed. Abstraction of physical effects using ternary algebra can guarantee the generation of valid tests.