Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units
Tero Säntti, Jouni Isoaho · 2002
In this paper a modified basic cell for wave-pipelines is proposed. The cell is self resetting and has complementary outputs. Simulations of the cell demonstrate that delay variations for all input combinations are small, and the cell's sensitivity to pulse length variation is reduced. 8/spl times/8 and 16/spl times/16-bit multipliers are designed using 0.35 /spl mu/m 2.5 V CMOS technology. The proposed units display a cycle time of 620 ps, corresponding to maximum operation frequency of 1.6 GHz.