Bit-level designer's assistant-a knowledge based approach to systolic processor design
A. Sarkar, S. Bandyopadhyay, GRAHAM A. JULLIEN · 2002
A knowledge-based system for the design of high-performance bit-level systolic arrays in VLSI is described. The design objectives are to give users an extensible system, where tutorial help is available through elaborate explanation facilities and to act as an input specification tool. An expert system shell has been used to create the knowledge base.>