An novel solution for testing power and testing time
Lei Xu, Yihe Sun, Hongyi Chen · 2002
An advanced scan array architecture considering testing power reduction is proposed, in which a wrapper and two dimensional scan chain is adopted. Furthermore pseudo-BIST is integrated with the wrapper to cut down the testing time. Experimental results of industrial circuits show that testing power is reduced, observable and is close to the functional power. At the same time, testing time is also cut down deriving benefits from pseudo-BIST.