FPGA-Based Variable Length Decoders.
Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha · 2003
A straightforward and fair comparison of variable length decoders is extremely difficult due to different implementation approaches, e.g., different codeword tables, IC technologies, design styles, and compression ratios. On the other hand, reconfigurable platforms provide fast design iteration times to change the design variables. Therefore, the variable rate symbol-parallel Variable Length Decoding (VLD) approach has been compared to FPGA-based variable length decoders presented in literature. The behavioural non-optimized VHDL model of the decoder has been mapped onto the FPGAs used in the references in order to guarantee same technological features. The variable rate symbol-parallel decoder provides 16-100 % better throughput at 2-3.6 times lower frequencies than the referenced designs. 1.