Testing of VLSI regular arrays
William Peter Marnane, Will R. Moore · 2003
The authors present a unifying approach to testing fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. This method can meet the requirements of any single-cell fault model and can cope with restricted access to the boundary of the array. It is shown how existing concepts such as C-testability can be utilized in generating test patterns.>