Development of a CMOS switched-capacitor instrumentation amplifier
G. Toffolo, P. Yick, Neil M. White · 1992
Summary form only given. Outlines the design and simulation of an instrumentation amplifier analogue cell for incorporation into an ASIC sub-system for smart sensors. The ASIC will be fabricated using ES2's 1 mu m CMOS n-well process. The existing analogue library for this process does not contain high specification devices which can be used as low-frequency programmable gain instrumentation amplifiers. Target requirements for the device include a low offset voltage drift, digital controllable gain selection, high CMRR and good power supply rejection. CMOS capacitors tend to show improved tolerances (+or-0.1%) and low temperature coefficients (10-50ppm/ degrees C). For these reasons a switched capacitor circuit configuration has been adopted. MOS transistors also possess the advantage of exhibiting near-zero voltage offset when configured as an analogue switch. >