Efficient FFT implementation on an IEEE floating-point digital signal processor
K.L. Kloker, Brett L. Lindsley, N. Baron, G. Sohie · International Conference on Acoustics, Speech, and Signal Processing · 2003
The authors describe the implementation of real and complex FFT (fast Fourier transform) algorithms on the Motorola DSP96002. The DSP96002 is a general-purpose, dual-bus IEEE standard floating-point digital signal processor (DSP). At a 74-ns instruction cycle, the DSP96002 implements a 1024-point real FFT in 0.905 ms and a 1024-point complex FFT in 1.55 ms. This performance is achieved by calculating up to three floating-point results in a single instruction cycle, or 40.5 MFLOPS peak. A radix-2 FFT butterfly is executed every four cycles, an average of 33.75 IEEE MFLOPS. The instruction set and architecture of the DSP96002 provide the basis for efficient implementation of FFTs and other fast transforms, such as the discrete Walsh-Hadamard transform, discrete cosine transform, and discrete Hartley transform.>