A low-power H.264/QVC decoder
Ting‐An Lin, Tsu-Ming Liu, Chen‐Yi Lee · 2005
In this paper, memory access could be saved in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In the proposed hierarchical syntax parser, gated clock technique could be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.