Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP
Kuei-Ming Lu, Kiichiro Tamaru · Proceedings of the ... International Symposium on Parallel Architectures, Algorithms, and Networks (ISPAN) · 2002
We know that a significant advantage of content addressable memory (CAM) is that operations are performed locally, thus it can eliminate the problem of bottleneck between processor and memory. In this paper, we propose a CAM-based associative processing processor (HAPP) which is able to combine with a general processor to form an array-processor system, and besides retrieval operations, it can assist the general processor to manipulate nested loop structure with data-flow dependence for achieving high speedup in this system. We enumerate some problems of applying HAPP to a computer system to deal with nested loop structure, and the methods we used to resolve them. Also we compare HAPP with a parallel machine, BBN TC2000, to prove that HAPP gains a smaller communication penalty when the number of data items access of BBN TC2000 surpasses penalty plane. >