Test considerations for BiCMOS logic families
K. Roy, M.E. Levitt, Jacob A. Abraham · 2002
The testability of various BiCMOS logic families is examined. For each design style the adequacy of stuck-at and quiescent current testing is explored. It is shown that while stuck-at and I/sub ddq/ testing can cover many faults there are still a large number of faults that are not detectable. Using the results presented the various logic families can be ranked by testability when being evaluated for an application.>