The implementation of an all digital speech synthesizer using a multimicroprocessor architecture
C. Hodges, Thomas P. Barnwell III, D. McWhorter · 2005
This paper presents a unique approach for the implementation of the speech synthesis portion of a LPC vocoder. The implementation uses eight LSI-11 microprocessors operating synchronously around a time division multiplexed multiport memory. The implementation of the recursive digital filter portion of the LPC synthesis is accomplished without the use of any high speed external arithmetic elements and in a way which requires no synchronization overhead. This particular technique illustrates a general procedure which is applicable to the implementation of a large class of digital signal processing algorithms on multiprocessor machines.