Block sequential CORDIC architectures
M. Sauer, E. Bernard, Josef A. Nossek · 1993 IEEE International Symposium on Circuits and Systems · 2002
In the design of VLSI circuits for parallel algorithms, a tradeoff between hardware complexity and execution speed often has to be made. This results in a decision between bit-parallel and bit-serial arithmetic implementations. A data format, called block data format, is used. It covers the whole range from bit-serial to bit-parallel processing and thus offers more flexibility in the decision process. Architectures for partitioned coordinate rotations digital computer (CORDIC) units are proposed. They are described using the blockwidth of the partitioned data record as a parameter, and are suited for a possible automatic layout generation of such modules. The partitioned data arrays additionally lead to a reduction of the maximal shift distance between two CORDIC stages from O(p) to O(/spl radic/p), where p is the wordlength of the operands, and thus reduce the maximal propagation delay. >