Test and repair of embedded flash memories
J.M. Daga · 2003
Summary form only given. Flash and EEPROM memories are now embedded in a large number of specific applications requiring a broad range of memory sizes. If full parallel access is possible the flash memory should be tested as a stand-alone memory. Controllability and observability are optimum, making test and characterization faster and easier. Unfortunately this approach results in an unacceptable pin count for the chip. Using a serial test interface (STI) dramatically reduces the pin count to an acceptable value, making the use of a STI a cost-effective solution for embedded flash testing. For SOCs having a very limited pin count, or high security constraints such as many smart card chips, test of the flash memory should be entirely generated on chip. One effective solution that has been implemented uses a ROM memory to store test patterns that are applied to the memory by the microcontroller. Memory outputs are then compared to expected ones. Regarding repair of embedded flash memories, redundancy should be considered as a way to improve yield. Error correcting codes (ECC) should be considered to improve reliability. This solution will be implemented for applications requiring a high level of programming endurance.