MPEG2 decoding complexity regulation for a media processor
Tse-Hua Lan, Yingwei Chen, Zhun Zhong · 2002
Current implementations of real-time video decoders employ hard-decoding without run-time computation regulation. The result is fluctuation in the video decoding time that requires over-specified dedicated hardware or general-purpose processors to guarantee real-time performance. We propose a computation regulation system for MPEG-2 video decoding on media processors that obviates over-engineering while maintaining real-time performance and video quality. Our computation regulation scheme consists of dynamic complexity prediction and control. The complexity prediction algorithm takes implementation issues specific to media processors into account and yields accurate prediction results that correlate with actual measurements to 97%. The predicted complexity is then used as a control signal to adjust the decoding algorithm so that peaks in computation load are suppressed. Simulation results show that our system can lower the overall CPU cycle budget by a large factor (25%) with very little degradation in video quality.