Architectural considerations for SF-core based microprocessor
A. Shachamm, Y. Levy, Zvika Bronstein, E. Loewenstein, D.M. Bruck, D. Deitcher · 2002
The newest member of National Semiconductor's Series 32000/EP family of Embedded System Processors is a 100 MIPS superscalar RISC microprocessor incorporating over 1,000,000 transistors. It contains a RISC core, called the SF-core, and additional modules integrated on the same chip. The SF-core incorporates two integer units, an optional IEEE-754 compatible floating-point unit (FPU), digital signal processing (DSP) enhancements, and instruction and data caches. Additional integrated modules are a two-channel direct memory access (DMA) controller, a 15-level interrupt control unit (ICU) and a 16-bit timer. The system interface is optimized to support high-performance cost-sensitive designs, achieving a peak performance of 100 MIPS/50 MFLOPS in 25 MHz systems. Due to its DSP capabilities, the SF-core performs 1024 points integer FFT in 1498 mu s and 1024 points floating-point FFT in 1025 mu s. Other features support multiprocessing and fault-tolerant systems. This microprocessor is fabricated in a 0.8 mu m dual-metal CMOS process.>