An efficient architecture for adaptive progressive thresholding
Haicheng Tian, Siew-Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang · Asia Pacific Conference on Circuits and Systems · 2003
A new pipelined architecture for adaptive progressive thresholding (APT) is proposed. Unlike the conventional architectures that rely heavily on multipliers and dividers to evaluate the maximum between-class variance, our method employs a reconfigurable logarithmic computing unit to simplify the circuitry and increases the application's ability to handle operational variation. Our logarithmic conversion algorithm avoids large look-up tables by streaming the operand's bits into segments so that several small look-up tables and simple adders and shifters are sufficient to guarantee an accurate result. Besides being cost effective, the proposed architecture has also significantly reduced the latency of the critical pipelined stage.