PLA based synthesis and testing of hazard free logic
U.K. Bhattacharyya, I. Sen Gupta, Sourav Kumar Nath, Pranab Kumar Dutta · 2002
This paper presents a divide and conquer approach for the hazard-free realization of combinational networks. The circuit is partitioned into a set of supergates which are individually made hazard-free. Since each supergate has to be implemented in two-level form, the circuit can be implemented as a multilevel network of PLAs. A modified supergate partitioning for multi-output circuits has also been proposed. Experiments to evaluate the testability of the synthesized circuits have been carried out.