TLB-only paging on x86-64
Martin Van Rijswick, Steffen Gerhold, Thilo Schmitt, Peter Schulthess · The 33rd International Convention MIPRO · 2010
In contrast to MIPS and Alpha, the x86-64 platform enforces a specific layout of the page table memory structures. We present a way to emulate the behavior of a MIPS TLB-miss exception on commodity x86-64 hardware. This offers new possibilities to operating system designers as they are free to choose more suitable memory data structures from the perspective of the specific operating system. We show that a page table structure consisting of 6 tables with 4 KB each is sufficient and minimal for this emulation. Additionally we describe a prototype implementation and present measurement results.