A JBIG arithmetic coder-decoder chip
Po Tong, P. Ang · 2003
A Joint Bilevel Image Experts Group (JBIG) arithmetic coder-decoder chip is presented. In addition to arithmetic coding, the chip also performs probability estimation for adaptation. With a 40-MHz clock, this half-duplex chip can process 8 Mb of raw data per second. The throughput is the same for both encode and decode operations, and is independent of the compression ratio. The chip is fabricated using a CMOS 1- mu m compacted array technology. Tests indicate that the chip is fully functional.>