An analog parallel processor for the dynamic programming paradigm
Krishnamurthy Soumyanath, J. Von Arx · 2003
A novel analog parallel approach to the implementation of the dynamic programming paradigm is described. The approach has been used to design a test chip which solves the single source, shortest path problem in a fully connected eight-mode network. The distributed processor design has been fabricated in a 2- mu m double poly low noise CMOS process using a die area of 2.22*2.22 mils. The design has a typical setting time of 100 ns and a worst case power dissipation of 3.5 W.>