Formal verification of DSP VLSI architectures: a tutorial
Khaled M. Elleithy, M.A. Hummaigani · 2002
In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approach is explained using one or more of the currently available systems.