Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers
Jong‐Sun Kim, Zhiwei Xu, Mau-Chung Frank Chang · 2003
This paper presents a new multiple access bus interface for re-configurable memory systems based on Code-Division-Multiple-Access (CDMA) techniques. It features multiple I/O access by using a multi-level signaling with source synchronous clocking. New CDMA I/O transceivers capable of re-configuring multiple accesses with high bus concurrency, low bus latency and low channel power consumption are proposed and evaluated. A maximum data rate of 2.0 Gbps/pin has been achieved using a 0.18-um CMOS process and a supply voltage of 1.8 V.