x86‐Android performance improvement for x86 smart mobile devices
Min Choi, Seung‐Ho Lim · Concurrency and Computation Practice and Experience · 2014
Summary With more and more smartphones with Intel inside available, the compatibility issues of Android applications have been rising. The efficiency on the emulated architecture is best translated into efficiency on the target machine if target instructions also operated on register operands. However, conventional binary translators of popular binary translators do not take into account instruction dependency among two or more basic blocks. This results in performance degradation because of intertranslation block dependency. Actually, x86 binary translators do not take into account instruction dependency within a basic block. Binary translation makes use of one or two registers for the majority of translation blocks. This is because the translation block corresponds to a guest instruction, which in turn the amount of work is not large. Even though there are no dependencies between translation blocks, false dependencies are generated by the same register usage order. In order to maximize the parallelism within a basic block, we maintain two different register usage orders, applying them in turn. This approach resolves the problem and outperforms conventional approach by up to around 27% for some cases. Copyright © 2014 John Wiley & Sons, Ltd.