ASIC Implementations of the Block Cipher SEA for Constrained Applications
François Macé, François‐Xavier Standaert, Jean-Jacques Quisquater · 2007
Abstract. SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards or processors. In this paper, we investigate its hardware performances in a 0.13 µm CMOS technology. For these purposes, different designs are detailed. First, a single clock cycle per round loop architecture is implemented. Beyond its low cost performances, a significant advantage of the proposed encryption core is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. Second, a more realistic design with a reduced datapath combined with a serial communication interface is described in order to put forward the low-power opportunities of SEA. Finally, a minimum datapath is presented and its applicability to RFID encryption is discussed. Additionally to these results, performance comparisons with the AES Rijndael are proposed. They illustrate the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency. 1