Digit-serial systolic power-sum array in GF(2/sup m/)
Keon-Jik Lee, Kee-Won Kim, Kee-Young Yoo · 2002
This paper presents a novel digit-serial-in-serial-out systolic array for performing the power-sum operation C+AB/sup 2/ in finite fields GF(2/sup m/) with the standard basis representation. If the appropriate digit-size is selected, the proposed method can meet the throughput requirement of a specific application with minimum hardware. With the digit size of the regular square form, the latency of the array can be reduced by 20% as before in GF(2/sup 160/). The new digit-serial systolic array with unidirectional data flow is highly regular, nearest-neighbor connected, and thus is well suited for VLSI implementation.