RESORT: a gate-level rule-based expert system optimization with resizing and testability enhancement
J.S. Wang, F. Lai · International Symposium on VLSI Technology, Systems, and Applications · 2003
A rule-based expert system for CMOS (complementary-metal-oxide semiconductor) combinational logic optimization is presented. The system, called RESORT (Rule-based Expert System Optimization with Resizing and Testability enhancement), accepts a gate-level description of a combinational logic circuit as input and generates a functionally equivalent one with delay and area within specified constraints. The actions of RESORT are similar to those performed by logic designers in transistor resizing and logic pattern replacement during manual optimizations. Testability enhancement (redundancy elimination) is also provided by RESORT. Because the optimizing rules in the rule base come from the expertise of the logic designers, the resulting circuit is not only close to the optimal outcome but also practical.>