Bridging the gap between precise RT-level power/timing estimation and fast high-level simulation : a method for automatically identifying and characterising combinational macros in synchronous sequential systems at register-transfer level and subsequent executable high-levelmodel generation with respect to non-functional properties
Kai Hylla · 2014
This thesis tackles the problem of a fast, yet accurate power and timing estimation of embedded HW modules at a high-level of abstraction. By augmenting an executable high-level model with accurate power and timing information, fast and comprehensive simulations at a high-level of abstraction become possible. Using HLS, a behavioural system description is transformed into a cycle-accurate description at RTL. Combinational macros are identified and characterised automatically, using sophisticated RT-level power models. These provide accurate estimates, while considering as many relevant physical properties and synthesis artefacts as possible. A power and timing annotated high-level simulation model is then generated. This virtual prototype allows a fast, yet accurate estimation of the design. The generated prototype can also be embedded into a virtual system prototype allowing a DSE, far more complex and comprehensive than would be feasible before. Evaluation results show that by having an average relative error per cycle of less than 6.93% and a total error of around 1%, a speed-up of 160x is archived, while giving nearly cycle-accurate estimates.