A VLSI architecture for discrete wavelet transform
Xuyun Chen, Ting Zhou, Qianling Zhang, Wei Li, Hao Min · 2002
The discrete wavelet transform (DWT) has received considerable attention in the context of image processing due to its temporal and frequency characteristics. A specific VLSI architecture for the forward/inverse DWT is presented. The characteristics of the structure and coefficients are utilized to reduce the circuit area. In addition, the Booth algorithm and balanced pipelines have been adopted which result in a high throughput at 2 outputs per clock and 5 clocks' pipeline latency. This design described and verified by the VHDL is synthesized by the Synopsys synthesizer. The synthesis results show that the gate-level circuit contains 5058 gates and the throughput can reach 110 M points/s when LSI 10 K CMOS technology is used.