A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor
Pak-Keung Leung, Chiu‐Sing Choy, Cheong-Fat Chan, Kong‐Pang Pun · 2003
Elliptic curve cryptography is becoming popular in recent decades due to its high security strength per bit, less memory resources and low processing power which makes it attractive for application in energy constraint applications such as contact-less smart cards. In this paper, a 173-bit (m = 173) Type II Optimal Normal Basis (ONBII) representation is chosen in the implementation of the Galois Field GF(2/sup m/) arithmetic logic unit by asynchronous architecture. This proposed architecture uses the advantages of asynchronous properties and is especially aimed at low power consumption by reducing the switching activities in the latches, reducing the number of cycles to complete each multiplication process and reducing the number of squaring operations in each inversion process. The simulation results show that the resulting ALU consumes only 110.8 nW in 780 ns to complete each multiplication operation.