Design of a 64-processor by 128-memory crossbar switching network
Robert F. Miracky, Alfred Hartmann, L. N. Smith, Steve Redfield, Uttam Ghoshal, B. Weigler · 2003
The authors describe the design of a 64-processor by 128-memory CMOS crossbar switching network that establishes working performance and density limits of a medium-scale ideal network. The design is based on advanced packaging technology utilizing tape-automated bonding of integrated circuit components to 3.25"-square high-density interconnect substrates. The maximum available data transfer bandwidth is 5.12 Gb/s. Minimum end-to-end latency to read a 40-bit memory word is 450 ns, while minimum write latency is 300 ns. The expected end-to-end latencies after correcting for contention (assuming uniform access probabilities) are 570 ns and 380 ns, respectively, for the case in which all memory accesses go through the network.>