The testability features of the 3rd generation ColdFire/sup (R)/ family of microprocessors
Alfred L. Crouch, Michael Mateja, Teresa McLaurin, John C. Potter, Duong Duy Tran · 2003
A description of the DFT and test challenges faced, and the solutions applied, to the newest member of the ColdFire/sup (R)/ microprocessor family, the MCF5307, is described. The MCF5307 is the first member of the family to have on-chip, PLL-sourced, dual clock domains where the bus interface and the internal core microprocessor operate at different, but selectable, frequency ratios; and the internal microprocessor core of the MCF5307 was designed as a separate stand-alone core that contained multiple embedded memory arrays. The DFT challenges and solutions described involve the development of the at-speed AC scan test architecture and scan vectors in a multiple clock domain environment; the application of memory BIST to multiple embedded memories in a cost effective manner; and the handling of an on-chip PLL clock source.