Using integer equations to check PSL properties in RT level design
Bijan Alizadeh, Zainalabedin Navabi · IEEE International Workshop on System-on-Chip for Real-Time Applications · 2004
This article describes a high level model of digital circuits for application of formal verification properties at this level. In our method, a behavioral state machine is represented by a multiplexer based structure of linear integer equations, and a subset of PSL property language is directly applied. It reduces the need for large BDD data structures and uses far less memory. Furthermore, there is no need to separate the data and control sections in circuits. We used a canonical form of linear TED (Ciesielski et al., 2002). This paper compares our results with those of the VIS verification tool which is a BDD based program.