The Performance of SCI Memory Hierarchies
Roberto A. Hexsel, Nigel P. Topham · 1994
This paper presents a simulation-based performance evaluation of a shared-memory multiprocessor using the Scalable Coherent Interface (IEEE 1596). The machines are assembled with one to 16 processors connected in a ring. The multiprocessor's memory hierarchy consists of split primary caches, coherent secondary caches and memory. For a workload of two parallel loops and three thread-based programs, secondary cache latency has the strongest impact on performance. For programs with high miss ratios, 16-node rings exhibit high network congestion whereas 4and 8-node rings perform better. With these same programs, doubling the processor speed yields between 20 and 70% speed gains with higher gains on the smaller rings.