2-D DWT/IDWT processor design for image coding
Xuyun Chen, Zhou Ting, Zhang Qian-lin, Min Hao · 2002
In this paper, a VLSI architecture for forward/inverse 2-D discrete wavelet transform is presented. This design described and verified by the VHDL is synthesized by the Synopsys-synthesizer. The synthesis results show that the gate-level circuit contains 7140 gates and the throughput can reach 4 M pixel/s when LSI 10 K CMOS process technology is used.