Scan test sequencing hardware for structural test
Jamie S. Cullen · 2002
This paper introduces a new hardware implementation for scan test sequencing within a tester. Instead of providing a monolithic scan memory with linear readback capabilities, the proposed test architecture uses dedicated scan test sequencing hardware to provide "on-the-fly" scan test sequencing. The approach is aimed not only at providing a more flexible test hardware solution, but at reducing the cost of structural test by significantly reducing scan memory size requirements.