CUSTOM GRAPHICAL SIMULATORS FOR VHDL LOGIC DESCRIPTIONS AND THE ALTERA NIOS II PROCESSOR
Naraig Manjikian, Valerie Sugarman · Proceedings of the Canadian Engineering Education Association (CEEA) · 2013
This paper describes the rationale for devel- oping custom graphical simulators for courses in digital logic and computer architecture, discusses key features of these simulators in relation to the laboratory hardware for the two courses in question, and explores the learning benefits that can be obtained. The digital logic simulator models switch/pushbutton inputs and LED outputs, and it allows a custom circuit to be specified rapidly in a subset of the VHDL language using predefined signal names and flip-flop elements. The computer architecture simulator provides higher-level modeling of the execution behavior of a 32-bit processor with graphical depiction of register and memory contents. It simulates character input/output, and it models the switch, pushbutton, and LED features of laboratory hardware. When students in the two courses were surveyed about the custom simulators, a majority of them indicated a degree of enhancement to their learning.