An application specific DSP chip set for 100 MHz data rates
S.S. Magar, S. Shen, G. Luikuo, M. Fleming, R. Aguilar · 2003
A 1.2- mu m CMOS chip set (processor and controller) has been designed for applications in high-performance fast Fourier transform (FFT)-based digital signal processing (DSP) systems. The processor chip performs about 500 million arithmetic operations per second and operates at an I/O rate of 5 billion bits per second. The controller chip provides total system control for FFT-based DSP systems. Algorithms such as FFT, spectrum analysis, digital filtering (via frequency domain) can be defined on the chip set by coding 5 to 10 instructions in the controller. Although a single chip set can process data rates at very high speeds (e.g. 1 K FFT in 16 mu s), multiple stages can be cascaded very simply for extremely high performance (up to 100-MHz data rates).>