A Chip-ID generating circuit for dependable LSI using random address errors on embedded SRAM and on-chip memory BIST
Hiroshi Fujiwara, Makoto Yabuuchi, Hiroki Nakano, H. Kawai, Koji Nii, Kazutami Arimoto · 2011
A chip-ID generating scheme with high-tamper resistance is proposed. This enables to extract a unique finger print from each chip by using random failure bits in an SRAM under the ID generation mode, and on-chip memory BIST. The stability and average of Humming distance of 128 bit ID become 99.9999999% and 63.9, respectively. The proposed scheme does not require any additional hardware IPs.